View M464S0924DTS_402978.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M464S0924DTS
M464S0924DTS SDRAM SODIMM
PC133/PC100 SODIMM
8Mx64 SDRAM SODIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION
The Samsung M464S0924DTS is a 8M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M464S0924DTS consists of four CMOS 8M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 144-pin glassepoxy substrate. Three 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M464S0924DTS is a Small Outline Dual In-line Memory Module and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. * * * * *
FEATURE
* Performance range Part No. M464S0924DTS-L7C/C7C M464S0924DTS-L7A/C7A M464S0924DTS-L1H/C1H M464S0924DTS-L1L/C1L Max Freq. (Speed) 133MHz (7.5ns @ CL=2) 133MHz (7.5ns @ CL=3) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3)
Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * Serial presence detect with EEPROM * PCB : Height (1,000mil) , double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 Pin 51 53 55 57 59 Front DQ14 DQ15 VSS NC NC Pin 52 54 56 58 60 Back DQ46 DQ47 VSS NC NC Pin Front DQ21 DQ22 DQ23 VDD A6 A8 V SS A9 A10/AP VDD DQM2 DQM3 V SS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 V SS **SDA VDD Pin Back 95 97 99 101 103 105 Voltage Key 107 109 CLK0 62 CKE0 111 VDD 64 VDD 113 RAS 66 CAS 115 WE 68 *CKE1 117 CS0 70 *A12 119 *CS1 72 *A13 121 DU 74 *CLK1 123 VSS 76 VSS 125 NC 78 NC 127 NC 80 NC 129 VDD 82 VDD 131 DQ16 84 DQ48 133 DQ17 86 DQ49 135 DQ18 88 DQ50 137 DQ19 90 DQ51 139 VSS 92 VSS 141 DQ20 94 DQ52 143 96 DQ53 98 DQ54 100 DQ55 102 VDD 104 A7 106 BA0 108 V SS 110 BA1 112 A11 114 VDD 116 DQM6 118 DQM7 120 V SS 122 DQ56 124 DQ57 126 DQ58 128 DQ59 130 VDD 132 DQ60 134 DQ61 136 DQ62 138 DQ63 140 V SS 142 **SCL 144 VDD
PIN NAMES
Pin Name A0 ~ A11 BA0 ~ BA1 DQ0 ~ DQ63 CLK0 CKE0 CS0 RAS CAS WE DQM0 ~ 7 VDD VSS SDA SCL DU NC Function Address input (Multiplexed) Select bank Data input/output Clock input Clock enable input Chip select input Row address storbe Column address strobe Write enable DQM Power supply (3.3V) Ground Serial data I/O Serial clock Dont use No connection
61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 Sept. 2001
M464S0924DTS
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select
PC133/PC100 SODIMM
Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+t SS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A11
Address
BA0 ~ BA1 RAS
Bank select address Row address strobe
CAS
Column address strobe
WE
Write enable
DQM0 ~ 7 D Q0 ~
63
Data input/output mask Data input/output Power supply/ground
VDD /VSS
Rev. 0.1 Sept. 2001
M464S0924DTS
FUNCTIONAL BLOCK DIAGRAM
CS0 DQM0 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM4
PC133/PC100 SODIMM
U0
LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
CS
U2
DQM2 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A0 ~ A11, BA0 & 1 RAS CAS WE CKE0 10 DQn V DD Three 0.1uF X7R 0603Capacitors per each SDRAM Vss To all SDRAMs Every DQ pin of SDRAM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SDRAM U0 ~ U3 CS
DQM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS
U1
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7
U3
DQM3
Serial PD
SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3
SCL 47K
WP SA0 SA1 SA2
SDA
U0 CLK0 U1 U2 U3 10 CLK1 10pF
Note : Use a zero ohm jumper to isolate A12 from the SDRAM pins in non-256Mbit designs.
Rev. 0.1 Sept. 2001
M464S0924DTS
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on V DD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS
PC133/PC100 SODIMM
Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 4 50 Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70C) Parameter Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Symbol V DD V IH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDDQ +0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN V DDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200 mV) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT Min 15 15 15 15 15 10 10 Max 25 25 25 21 25 12 12 Unit pF pF pF pF pF pF pF
Parameter Input capacitance (A0 ~ A11, BA0 ~ BA1) Input capacitance (RAS , CAS, WE) Input capacitance (CKE0) Input capacitance (CLK0) Input capacitance (CS0 ) Input capacitance (DQM0 ~ DQM7) Data input/output capacitance (DQ0 ~ DQ63)
Rev. 0.1 Sept. 2001
M464S0924DTS
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T A = 0 to 70C) Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE V IL(max), tCC = 10ns CKE & CLK V IL(max), tCC = CKE V I H(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE V I H(min), CLK VIL(max), tCC = Input signals are stable CKE V IL(max), tCC = 10ns CKE & CLK V IL(max), tCC = CKE V I H(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE V I H(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
PC133/PC100 SODIMM
Version Test Condition -7C -7A -1H -1L Unit Note
Parameter
Operating current (One bank active) Precharge standby current in power-down mode
ICC1
440
400
400
400
mA
1
ICC2P ICC2PS ICC2N
8 mA 8 80 mA 40 20 mA 20 120 mA
Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode ICC3P ICC3PS ICC3N
Active standby current in non power-down mode (One bank active)
ICC3NS
100
mA
Operating current (Burst mode)
ICC4
560
560
520
520
mA
1
Refresh current Self refresh current
ICC5 ICC6
880
800 8 3.2
760
760
mA mA mA
2
Rev. 0.1 Sept. 2001
M464S0924DTS
AC OPERATING TEST CONDITIONS (V DD = 3.3V 0.3V, TA = 0 to 70C)
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
PC133/PC100 SODIMM
Unit V V ns V
3.3V
Vtt = 1.4V
1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol - 7C tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 60 65 2 2 CLK + tRP 1 1 1 2 1 15 15 15 45 15 20 20 45 100 70 70 Version - 7A - 1H 20 20 20 50 -1L 20 20 20 50 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2,5 5 2 2 3 4 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 0.1 Sept. 2001
M464S0924DTS
PC133/PC100 SODIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 3 3 2.5 2.5 1.5 0.8 1 5.4 5.4 tSAC Symbol Min CLK cycle time CLK to valid output delay Output data hold time tCC 7.5 7.5 5.4 5.4 3 3 2.5 2.5 1.5 0.8 1 5.4 6 - 7C Max 1000 Min 7.5 10 5.4 6 3 3 3 3 2 1 1 6 6 - 7A Max 1000 Min 10 10 6 6 3 3 3 3 2 1 1 6 7 ns ns ns ns ns ns 3 3 3 3 2 - 1H Max 1000 Min 10 12 6 7 ns 2 ns 1,2 - 1L Max 1000 ns 1 Unit Note
CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 0.1 Sept. 2001
M464S0924DTS
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H
CKEn-1 CKEn CS RAS CAS
PC133/PC100 SODIMM
(V=Valid, X=Dont care, H=Logic high, L=Logic low)
WE DQM BA0,1 A10/AP A11, A9 ~ A 0 Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP code X
1,2 3 3
X X X V V
X Row address L H
Column address (A0 ~ A8 ) Column address (A0 ~ A8 )
3 3
Bank active & row addr. Read & column address Write & column address Burst stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
L L
4 4,5 4 4,5 6
H H H
X X X
L L L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.1 Sept. 2001
M464S0924DTS
PACKAGE DIMENSIONS
PC133/PC100 SODIMM
Units : Inches (Millimeters)
2.66 (67.56) 2.50 (63.60) 0.16 0.039 (4.00 0.10) (20 .0 0) 0.24 (6.0) 0.79
2-R 0.078 Min (2.00 Min) ( 25.40 ) 0.024 0.001 (0.600 0.050) 0.008 0.006 (0.200 0.150) 0.03 TYP (0.80 TYP)
1
59
61
143
0.13 (3.30)
0.91 (23.20)
0.10 (2.50)
0.18 (4.60) 0.083 (2.10)
1.29 (32.80)
2 - 0.07 (1.80)
Z 0.15 (3.70)
2 60 62 144
Y
0.150 Max (3.80 Max) (3.20 Min ) (4.00 Min ) 0 .1 25 Min 0.157 Min 0.16 0.0039 (4.00 0.10) 0.06 0.0039 (1.50 0.1)
0.04 0.0039 (1.00 0.10)
Detail Z
(2 .5 40 Min)
0 .1 00 Min
Detail Y
Tolerances : 0.006(.15) unless otherwise specified The used device is 8Mx16 SDRAM, TSOP SDRAM Part No. : K4S281632D
Rev. 0.1 Sept. 2001
1 .0 0
M464S0924DTS
M464S0924DTS-C7C/L7C/C7A/L7A/C1H/L1H/C1L/L1H
* * * * * * * * Organization : 8Mx64 Composition : 8Mx16 * 4 Used component part # : K4S281632D-TC7C/TL7C/TC75/TL75/TC1H/TL1H/TC1L/TL1L # of rows in module : 1 Row # of banks in component : 4 banks Feature : 1,000mil height & double sided component Refresh : 4K/64ms Contents ;
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function Described -7C # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly ...... Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @CAS latency of 3 SDRAM access time from clock @CAS latency of 3 DIMM configuraion type Refresh rate & type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes : Burst lengths supported SDRAM device attributes : # of banks on SDRAM device SDRAM device attributes : CAS latency SDRAM device attributes : CS latency SDRAM device attributes : Write latency SDRAM module attributes 2&3 7.5ns 5.4ns Function Supported -7A -1H
PC133/PC100 SODIMM
Hex value -1L -7C -7A 80h 08h 04h 0Ch 09h 01h 40h 00h 01h 10ns 6ns 75h 54h 75h 54h 00h 80h 10h 00h 01h 8Fh 04h 2&3 06h 06h 01h 01h 00h 06h 06h A0h 60h A0h 60h -1H -1L
Note
128bytes 256bytes (2K-bit) SDRAM 12 9 1 row 64 bits LVTTL 7.5ns 5.4ns 10ns 6ns
1 1
2 2
Non parity 15.625us, support self refresh x16 None tCCD = 1CLK 1, 2, 4, 8 & full page 4 banks 2&3 2&3
0 CLK 0 CLK Non-buffered, non-registered & redundant addressing +/- 10% voltage tolerance,
22
SDRAM device attributes : General
Burst Read Single bit Write precharge all, auto precharge
0Eh
23 24 25 26 27 28 29 30 31 32 33 34
SDRAM cycle time @CAS latency of 2 SDRAM access time from clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=t RCD) Minimum activate precharge time (=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time
7.5ns 5.4ns 15ns 15ns 15ns 45ns
10ns 6ns 20ns 15ns 20ns 45ns
10ns 6ns 20ns 20ns 20ns 50ns
12ns 7ns 20ns 20ns 20ns 50ns
75h 54h 00h 00h 0Fh 0Fh 0Fh 2Dh
A0h 60h 00h 00h 14h 0Fh 14h 2Dh 10h
A0h 60h 00h 00h 14h 14h 14h 32h
C0h 70h 00h 00h 14h 14h 14h 32h
2 2
1 row of 64MB 1.5ns 0.8ns 1.5ns 1.5ns 0.8ns 1.5ns 2ns 1ns 2ns 2ns 1ns 2ns 15h 08h 15h 15h 08h 15h
20h 10h 20h
20h 10h 20h
Rev. 0.1 Sept. 2001
M464S0924DTS
Byte # 35 36~61 62 63 64 65~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 128+ Function Described -7C Data signal input hold time Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code ...... Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (DIMM Configuration) Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) ...... Manufacturer part # (Data bits) Manufacturer part # (Mode & operating voltage) Manufacturer part # (Module depth) ...... Manufacturer part # (Module depth) Manufacturer part # (Refresh, #of banks in Comp. & Interface) Manufacturer part # (Composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (TBD) Manufacturer revision code (For PCB) ...... Manufacturer revision code (For component) Manufacturing date (Year) Manufacturing date (Week) Assembly serial # Manufacturer specific data (may be used in future) System frequency for 100MHz PC100 specification details Unused storage locations 7 C 7 A Blank S D-die (5th Gen.) Undefined 100MHz 0.8ns Function Supported -7A 0.8ns Intel Rev 1.2B Samsung Samsung Onyang Korea M 4 Blank 6 4 S 0 9 2 4 D T S "-" L/C 1 H -1H 10ns
PC133/PC100 SODIMM
Hex value -1L 10ns -7C 08h -7A 08h 00h 12h 65h A6h CEh 00h 01h 4Dh 34h 20h 36h 34h 53h 30h 39h 32h 34h 44h 54h 53h 2Dh 4Ch / 43h 1 L 37h 43h 37h 41h 20h 53h 44h 64h 8Fh 8Fh 8Fh 8Dh 3 3 4 31h 48h 31h 4Ch 0Dh 3Dh -1H 10h -1L 10h Note
Detailed PC100 Information Undefined
Note : 1. The row select address is excluded in counting the total # of addresses.
2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung s own Assembly Serial # system. All modules may have different unique serial #.
Rev. 0.1 Sept. 2001

▲Up To Search▲

Price & Availability of M464S0924DTS

	To Download M464S0924DTS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .